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module led_water_tb;

        //inputs
        reg sys_clk;
        reg sys_rstn;
       
        //outputs
        wire [7:0] led;
       
        //Instantiate the Unit Under Test (UUT)
        led_water led_water_inst(
         .sys_clk    (sys_clk),
         .sys_rstn   (sys_rstn),
         .led        (led)
        );
       
        initial begin
        // Initialize Inputs
        sys_clk=0;
        sys_rstn=0;
       
        //Wait 100ns for global reset to finish
        #100;
       
        sys_rstn=1;
       
end
always
        #10 sys_clk=~sys_clk;
endmodule