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自己写了一个写12864的状态机，但是编译之后显示资源利用为0，是全编译，但是就是查不到问题，请高手帮忙看一下！

module lcd12864(sys_clk,
sys_rst,
lcd_rs,
lcd_rw,
lcd_e,
lcd_dataout
);
 
input sys_clk;
input sys_rst;
output lcd_rs;
output lcd_rw;
output lcd_e;
output [7:0]lcd_dataout;


reg lcd_e;
reg lcd_rs;
reg lcd_rw;
reg [7:0]lcd_dataout;
wire [7:0]dataout_sbuff;


reg [14:0]clk_div_delay_cnt;


reg div_clk;


reg complete_flag;
reg[2:0]current_state;
reg[2:0]next_state;
reg setfunction_ok;
reg cleardisplay_ok;
reg setdisplaystate_ok;
reg display_ok;
reg [9:0]address_cnt;
wire [9:0]address;








parameter state_idle=3'b001;
parameter state_setfunction=3'b011;
parameter state_cleardisplay=3'b111;
parameter state_setdisplaystate=3'b110;
parameter state_display=3'b101;




always@(posedge sys_clk or negedge sys_rst)
begin
if(1'b0==sys_rst)
clk_div_delay_cnt<=15'd0;
else
if(15'd32000==clk_div_delay_cnt)
begin
clk_div_delay_cnt<=15'd0;
div_clk<=~div_clk;
end
else
clk_div_delay_cnt<=clk_div_delay_cnt+15'd1;
end




always@(posedge div_clk or negedge sys_rst)
begin
if(1'b0==sys_rst)
current_state<=state_idle;
else
if(1'b1==complete_flag)
current_state<=state_idle;
else
current_state<=next_state;
end




always@(current_state or setdisplaystate_ok or setfunction_ok or display_ok or cleardisplay_ok or complete_flag)
begin
case(current_state)
state_idle:
begin
if(1'b1==complete_flag)
next_state<=state_idle;
else
next_state<=state_setfunction;
end
state_setfunction:
begin
if(1'b1==setfunction_ok&&1'b1==complete_flag)
next_state<=state_idle;
else
next_state<=state_cleardisplay;
end
state_cleardisplay:
begin
if(1'b1==cleardisplay_ok&&1'b1==complete_flag)
next_state<=state_idle;
else
next_state<=state_setdisplaystate;
end
state_setdisplaystate:
begin
if(1'b1==setdisplaystate_ok&&1'b1==complete_flag)
next_state<=state_idle;
else
next_state<=state_display;
end
state_display:
begin
if(1'b1==display_ok&&1'b1==complete_flag)
next_state<=state_idle;
else
next_state<=state_display;
end
default:next_state<=state_idle;
endcase
end


always@(posedge div_clk )
begin
case(current_state)
state_idle:
if(1'b1==complete_flag)
lcd_e<=1'b0;
else
lcd_e<=1'b1;
state_setfunction:
begin
// lcd_e<=1'b1;
lcd_rs<=1'b0;
lcd_rw<=1'b0;
lcd_dataout<=8'b0011_0000;
setfunction_ok<=1;
end
state_cleardisplay:
begin
// lcd_e<=1'b1;
lcd_rs<=1'b0;
lcd_rw<=1'b0;
lcd_dataout=8'b0000_0001;
cleardisplay_ok<=1;
end
state_setdisplaystate:
begin
// lcd_e<=1'b1;
lcd_rs<=1'b0;
lcd_rw<=1'b0;
lcd_dataout<=8'b0000_1100;
setdisplaystate_ok<=1;
end
state_display:
begin
if(10'd1023==address_cnt)
begin
display_ok<=1;
complete_flag<=1'b1;
address_cnt<=10'd0;
end
else
begin
address_cnt<=address_cnt+10'd1;
lcd_e<=~lcd_e;
lcd_rs<=1'b1;
lcd_rw<=1'b0;
lcd_dataout<=dataout_sbuff;
end
end
default:complete_flag<=0;
endcase
end


assign address=address_cnt;


rom rom(.address(address),
.clock(sys_clk),
.q(dataout_sbuff)
);

endmodule