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3-3： 解：1、用IF_THEN语句实现4选1多路选择器 
LIBRARY  IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY  mux41 IS      
      PORT  (A,B,C,D,S0,S1,S2,S3: IN     STD_LOGIC;                                   
                    Y:       OUT STD_LOGIC); 
END     ENTITY  mux41; 
ARCHITECTURE  if_mux41    OF  mux41   IS 
    SIGNAL  S :STD_LOGIC_VECTOR(3   DOWNTO  0);
BEGIN
      PROCESS(S3,S2,S1,S0)
      BEGIN
           IF            S0="0"        THEN    Y    <=   A;
           ELSIF      S1="0"        THEN    Y   <=    B;
           ELSIF      S2="0"        THEN    Y     <=    C;             ELSIF     S3="0"          THEN   Y    <=    D;
           END   IF;
       END  PROCESS;
END ARCHITECTURE      if_mux41;
2、用CASE语句实现4选1多路选择器
LIBR ARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux41  IS
     PORT   (A,B,C,D,S0,S1,S2,S3;IN  STD_LOGIC
                    Y:       OUT  STD_LOGIC);
END  ENTITY  mux41;
ARCHITECTURE    case_mux41       OF  mux41     IS
SIGNAL  S :STD_LOGIC_VECTOR(3   DOWNTO  0);
BEGIN
      PROCESS(S3,S2,S1,S0)
         BEGIN
         CASE(S="0")   IS WHEN     "S0"   => Y<=A; WHEN     "S1"  =>Y  <=B; WHEN     "S2"  = >Y   <=C; WHEN     "S3"  => Y <=D; WHEN     OTHERS  =>NULL; END CASE; END  PROCESS; END   case_mux41;
3、用WHEN_ELSE语句实现4选1多路选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux 41 IS
     PORT     (A,B,C,D,S0,S1,S2,S3:IN STD_LOGIC;
                      Y:           OUT STD_LOGIC);
END ENTITY mux 41;
ARCHITECTURE  when_mux41    OF mux41    IS
  SIGNAL.S:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  PROCESS(S3,S2,S1,S0)
     BEGIN
          Y<=A  WHEN   S0="0" ELSE                 B   WHEN   S1="0" ELSE                 C   WHEN    S2="0"  ELSE                 D    WHEN   S3="0" ELSE NULL;    
   END ARCHITECTURE  when_mux41;

3-4

(1)

LIBRARY    IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_suber IS

       PORT(x,y,sub_in:           IN STD_LOGIC;

                  sub_out,diff_out:   OUT STD_LOGIC);

        END ENTITY  f_suber;

     ARCHITECTURE    fs1    OF  f_suber  IS

           COMPONENT  h_suber

                 PORT(x,y:         IN  STD_LOGIC;

                              diff,s_out:OUT STD_LOGIC);

                    END  COMPONENT;

                   SIGNAL a,b,c:STD_LOGIC;

             BEGIN

           u1:  h_suber  PORT MAP(x=>xin,y=>yin,      diff=>a,        s_out=>b);

           u2:  h_suber PORT MAP(x=>a,  y=>sub_in,diff=>diff_out,s_out=>c);

          sub_out <=c OR b;

      END ARCHITECTURE fs1; 

(2)图在附件里

程序

LIBRARY  IEEE;

  USE IEEE.STD_LOGIC_1164.ALL;

   ENTITY  suber_8 IS

             PORT (x0,x1,x2,x3,x4,x5,x6,x7:     IN STD_LOGIC;

                         y0,y1,y2,y3,y4,y5,y6,y7,sin:    IN STD_LOGIC;

                          diff0,diff1,diff2,diff3:     OUT STD _LOGIC;

                          diff4,diff5,fiff6,diff7,sout: OUT STD_LOGIC );

       END ENTITY suber_8;

      ARCHITECTURE s8 OF suber_8 IS

            COMPONENT  f_suber

               PORT(xin,yin,sub_in:              IN STD_LOGIC;

                          sub_out,diff_out:           OUT  STD_LOGIC);

           END COMPONENT;

            SIGNAL a0,a1,a2,a3,a4,a5,a6:  STD_LOGIC;

         BEGIN

         u0:   f_suber  PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0);

         u1:   f_suber   PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1);

         u2:   f_suber  PORT  MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2);

         u3:   f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3);

         u4:   f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4);

         u5:   f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5);

         u6:   f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6);

         u7:   f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout);

             END  ARCHITECTURE s8;