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3-3

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mux 41 IS

PORT (a,b,c,d:IN STD_LOGIC;

S0: IN STD_LOGIC;

S1: IN STD_LOGIC;

y: OUT STD_LOGIC);

END ENTITY mux 41;

ARCHITECTURE case_mux41 OF mux41 IS

SIGNAL.s0s1 :STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN

s0s1<=s1&s0;

PROCESS(s0s1,a,b,c,d)

BEGIN

CASE s0s1 IS

WHEN "00"

WHEN "01"

WHEN "10"

WHEN "11"

WHEN OTHERS

END CASE;

END PROCESS;

END ARCHITECTURE case_mux41;

3-4

(1)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_suber IS

PORT(x,y,sub_in: IN STD_LOGIC;

sub_out,diff_out: OUT STD_LOGIC);

END ENTITY f_suber;

ARCHITECTURE fs1 OF f_suber IS

COMPONENT h_suber

PORT(x,y: IN STD_LOGIC;

diff,s_out:OUT STD_LOGIC);

END COMPONENT;

SIGNAL a,b,c:STD_LOGIC;

BEGIN

u1: h_suber PORT MAP(x=>xin,y=>yin, diff=>a, s_out=>b);

u2: h_suber PORT MAP(x=>a, y=>sub_in,diff=>diff_out,s_out=>c);

sub_out <=c OR b;

END ARCHITECTURE fs1;

(2)图在附件里

程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY suber_8 IS

PORT (x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC;

y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_LOGIC;

diff0,diff1,diff2,diff3: OUT STD _LOGIC;

diff4,diff5,fiff6,diff7,sout: OUT STD_LOGIC );

END ENTITY suber_8;

ARCHITECTURE s8 OF suber_8 IS

COMPONENT f_suber

PORT(xin,yin,sub_in: IN STD_LOGIC;

sub_out,diff_out: OUT STD_LOGIC);

END COMPONENT;

SIGNAL a0,a1,a2,a3,a4,a5,a6: STD_LOGIC;

BEGIN

u0: f_suber PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0);

u1: f_suber PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1);

u2: f_suber PORT MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2);

u3: f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3);

u4: f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4);

u5: f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5);

u6: f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6);

u7: f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout);

END ARCHITECTURE s8;