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3-5 用 VHDL设计一个3-8译码器，要求分别用顺序赋值语句、case语句、if_else语句或移位操作符来完成。比较这4中方式中，哪一种最节省逻辑资源。    

答：

3-5 解（1）：顺序赋值语句

3到8译码器设计(顺序赋值语句实现)

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder3to8 IS 

port(DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

END decoder3to8; 

ARCHITECTURE behave OF decoder3to8 IS

BEGIN 

WITH CONV_INTEGER(DIN) SELECT

DOUT<="00000001" WHEN 0,

"00000010" WHEN 1,

"00001000" WHEN 3,

"00010000" WHEN 4,

"00100000" WHEN 5,

"01000000" WHEN 6,

"10000000" WHEN 7, 

UNAFFECTED WHEN OTHERS;

END behave;

（2）：case语句

3到8译码器设计(case语句实现)

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder3to8 IS 

port(DIN: IN

STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

END decoder3to8; 

ARCHITECTURE behave OF decoder3to8 IS

BEGIN 

PROCESS (DIN)

BEGIN 

CASE CONV_INTEGER(DIN) IS

WHEN 0 => DOUT<="00000001";

WHEN 1 => DOUT<="00000010";

WHEN 2 => DOUT<="00000100";

WHEN 3 => DOUT<="00001000";

WHEN 4 => DOUT<="00010000";

WHEN 5 => DOUT<="00100000";

WHEN 6 => DOUT<="01000000";

WHEN 7 => DOUT<="10000000"; 

WHEN OTHERS => NULL;

END CASE; 

END PROCESS;

END behave;

（3）：if_else语句

 3到8译码器设计(if_else语句实现)

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder3to8 IS 

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

END decoder3to8; 

ARCHITECTURE behave OF decoder3to8 IS

BEGIN 

PROCESS (DIN)

BEGIN 

IF CONV_INTEGER(DIN)=0 THEN DOUT<="00000001";

ELSIF CONV_INTEGER(DIN)=1 THEN DOUT<="00000010";

ELSIF CONV_INTEGER(DIN)=2 THEN DOUT<="00000100";

ELSIF CONV_INTEGER(DIN)=3 THEN DOUT<="00001000";

ELSIF CONV_INTEGER(DIN)=4 THEN DOUT<="00010000"; 

ELSIF CONV_INTEGER(DIN)=5 THEN DOUT<="00100000";

ELSIF CONV_INTEGER(DIN)=6 THEN DOUT<="01000000";

ELSIF CONV_INTEGER(DIN)=7 THEN DOUT<="10000000";

END IF;

END PROCESS;

END behave;

（4）：移位操作符

 3到8译码器设计(移位操作实现)

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY decoder3to8 IS 

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

END decoder3to8; 

ARCHITECTURE behave OF decoder3to8 IS

BEGIN 

DOUT<="00000001" SLL CONV_INTEGER(DIN);

END behave;

3-14 用循环语句设计一个7人投票表决器。

答：

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY vote_7 IS 

PORT( DIN:

IN STD_LOGIC_VECTOR(6 DOWNTO 0);

G_4: OUT STD_LOGIC;

CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));

END vote_7; 

ARCHITECTURE BHV OF vote_7 IS

BEGIN 

PROCESS(DIN) 

VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN 

Q:="000"; 

FOR n IN 0 TO 6 LOOP

IF(DIN(n)='1') THEN Q:=Q+1; END IF;

END LOOP;

CNTH<=Q; 

IF Q>=4 THEN G_4<='1'; ELSE G_4<='0'; END IF;

END PROCESS;

END BHV;