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习题3-4
（1）半减器
LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  h_suber  IS
     PORT (     x, y : IN  STD_LOGIC;
           diff, s_out : OUT  STD_LOGIC);
END  ENTITY  h_suber;
ARCHITECTURE  fh1  OF  h_suber  IS
BEGIN
      s_out <= (NOT x ) AND  y;
      diff <= x  XOR  y;
END  ARCHITECTURE  fh1;
(2)全减器
LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  f_suber  IS
     PORT ( X,Y,sub_in : IN  STD_LOGIC;
             diff,s_out : OUT  STD_LOGIC);
END  ENTITY  f_suber;
ARCHITECTURE  fd1  OF  f_suber  IS
COMPONENT  h_suber 
   PORT  (x ,y : IN  STD_LOGIC;  s_out ,diff : OUT  STD_LOGIC);
END  COMPONENT;
SIGNAL  net1, net2, net3: STD_LOGIC;
BEGIN
   u1 : h_suber  PORT  MAP(x=>X, y=>Y, diff=>net1, s_out=>net2);
   u2 : h_suber  PORT  MAP(x=>net1, y=>sub_in, diff=>diffr, s_out=>net3);
   sub_out <= net2  OR  net3;
END  fd1;