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-- Engineer:          skycanny
-- Module Name:    fulladder - Behavioral
-- Tool versions:  ISE 7.1 
-- Description:    This module is designed to discribe a full adder with carry
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder is
 port(
  reset : in std_logic;
  clk : in std_logic;
  operand1: in std_logic_vector(7 downto 0);
  operand2: in std_logic_vector(7 downto 0);
  carry : out std_logic;
  sum : out std_logic_vector(7 downto 0)
  );
end fulladder;

architecture Behavioral of fulladder is

begin

      process(reset,clk)
      variable sum_t : std_logic_vector(7 downto 0);
 variable carry_t: std_logic;
 begin
       if(reset = '0') then
   carry <= '0';
   sum <= (others => '0');
  elsif(rising_edge(clk)) then
   carry_t := '0';
   for i in 0 to 7 loop
    sum_t(i) := operand1(i) xor operand2(i) xor carry_t;
    carry_t  := (operand1(i) and operand2(i)) or (carry_t and (operand1(i) or operand2(i)));
   end loop;
  carry <= carry_t;
  sum <=  sum_t;
  end if;  
      end process;

end Behavioral;

通过对上述代码的综合（XST)，布局布线和后仿真，可以发现整个加法器是可以正常工作的。也没有毛刺的现象，避免了逻辑电路设计中最忌讳的一点。仿真时钟是100mhz。

      整个设计过程是这样的：首先写出一位全加器的真值表，根据真值表画出卡诺图，化简卡诺图，写出了sum和carry的逻辑表达式。然后根据逻辑表达式写出上面的RTL级的代码。可见基础的数电知识还是很重要的。估计现在很少有人卡诺图了吧。