2. Simple clock divider where the input clock is divided by an odd integer ................................ 4
3. Odd integer division with 50% duty cycle .................................................................................. 4
4. Non-integer division (duty cycle not 50%) ................................................................................. 6
4.1 Divide by 1.5 with duty cycle not exactly 50%........................................................................... 6
4.2 Divide by 4.5 with duty cycle not exactly 50% (counter implementation)..................................... 7
4.2.1 Verilog code for Divide by 4.5 ........................................................................................... 8
5 Alternative approach for divide by-N .......................................................................................... 9
5.1 Divide by 1.5 (LUT implementation)......................................................................................... 9
5.2 Divide by 2.5 (LUT Implementation)....................................................................................... 11
5.3 Divide by 3 with 50% duty cycle output................................................................................... 14
5.4 Divide by 5 with 50% duty cycle output................................................................................... 16
6. Conclusions ............................................................................................................................... 18
7. Acknowledgements ................................................................................................................... 18
8. References ................................................................................................................................ 18
9. Author & Contact information .................................................................................................. 19
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