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# vlog -vlog01compat -work work +incdir+F:/y1nG/altera/18.1/FSK_Dem/module/bpf1 {F:/y1nG/altera/18.1/FSK_Dem/module/bpf1/bpf1.vo}

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016

# Start time: 19:02:20 on Apr 16,2019

# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/y1nG/altera/18.1/FSK_Dem/module/bpf1" F:/y1nG/altera/18.1/FSK_Dem/module/bpf1/bpf1.vo 

# ** Error: (vlog-7) Failed to open design unit file "F:/y1nG/altera/18.1/FSK_Dem/module/bpf1/bpf1.vo" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 19:02:20 on Apr 16,2019, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

# ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

# Error in macro ./FSK_Dem_run_msim_rtl_verilog.do line 79

# C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

#     while executing

# "vlog -vlog01compat -work work +incdir+F:/y1nG/altera/18.1/FSK_Dem/module/bpf1 {F:/y1nG/altera/18.1/FSK_Dem/module/bpf1/bpf1.vo}"

FIR II 仿真出现上述错误，全编译是没有问题的。我到相应目录上也没看到有任何文件的产生。

如果我注释调用IP核代码全编译仿真，取消注释的代码全编译后，在ModelSim重新Recompile和Restart，才有FIR II 的仿真结果。请问有大佬遇过这种情况吗？我搞了好久都没有摸出个所以然。希望有大神可以回答一下。谢谢！