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FRDM-MCXA153开发板开箱试机

工程师
2026-09-12 12:52:29     打赏

1. 收货开箱

终于到货了,迫不及待的拆开快递。

 image.png

外包装是这样的。

 image.png

打开盒子里面的板子非常精美,并配有数据线。

 image.png

来个板子正方面的照片

image.png

image.png

2. 原理介绍

FRDM-MCXA153是一款紧凑且可扩展的开发板,可让您快速基于MCX A14和A15 MCU开展原型设计。它们提供行业标准的接口,可轻松访问MCU的I/O、集成的开放标准串行接口、外部闪存和板载MCU-Link调试器。通过MCUXpresso Developer ExperienceMCUXpresso开发人员体验)提供其他工具,如面向附加板的扩展板中心和面向软件示例的应用代码中心

image.png

开发板原理框图 

 

 

3. 验证测试

 

板子上电。

测试代码:

status_t PWM_SetupPwmPhaseShift(PWM_Type *base,

                                pwm_submodule_t subModule,

                                pwm_channels_t pwmChannel,

                                uint32_t pwmFreq_Hz,

                                uint32_t srcClock_Hz,

                                uint8_t shiftvalue,

                                bool doSync)

{

    assert(pwmFreq_Hz != 0U);

    assert(srcClock_Hz != 0U);

    assert(shiftvalue <= 50U);

 

    uint32_t pwmClock;

    uint16_t pulseCnt = 0, pwmHighPulse = 0;

    uint16_t modulo = 0;

    uint16_t shift  = 0;

 

    if (pwmChannel != kPWM_PwmX)

    {

        /* Divide the clock by the prescale value */

        pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT)));

        pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz);

 

        /* Clear LDOK bit if it is set */

        if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule)))

        {

            base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule);

        }

 

        modulo = (pulseCnt >> 1U);

        /* Indicates the start of the PWM period */

        base->SM[subModule].INIT = PWM_GetComplementU16(modulo);

        /* Indicates the center value */

        base->SM[subModule].VAL0 = 0;

        /* Indicates the end of the PWM period */

        /* The change during the end to start of the PWM period requires a count time */

        base->SM[subModule].VAL1 = modulo - 1U;

 

        /* Immediately upon when MCTRL[LDOK] being set */

        base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK;

 

        /* phase shift value */

        shift = (pulseCnt * shiftvalue) / 100U;

 

        /* duty cycle 50% */

        pwmHighPulse = pulseCnt / 2U;

 

        if (pwmChannel == kPWM_PwmA)

        {

            base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo) + shift;

            base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U;

        }

        else if (pwmChannel == kPWM_PwmB)

        {

            base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo) + shift;

            base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U;

        }

        else

        {

            return kStatus_Fail;

        }

 

        if (doSync)

        {

            /* Set LDOK bit to load VALx bit */

            base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule);

        }

    }

    else

    {

        return kStatus_Fail;

    }

 

    return kStatus_Success;

}



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