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三分频1：1占空比的VHDL程序（有一个缺点，输入波形必须是1：1的占空比，输出才符
合要求）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_down is
port(clk : in std_logic;
flag :out std_logic);
end counter_down;
architecture body_cout of counter_down is
signal cou1 ,cou2 : std_logic_vector(1 downto 0 );
signal flag1,flag2 : std_logic;
begin
process(clk)
begin
if(clk = '0' and clk'event) then
if(cou1 = "10") then
cou1 <= "00";
else
cou1 <= cou1 + '1';
end if;
end if;
end process;
process(clk)
begin
if(clk = '1' and clk'event) then
if(cou2 = "10") then
cou2 <= "00";
else
cou2 <= cou2 + '1';
end if;
end if;
end process;
process(cou1)
begin
if(cou1 = "01" ) then
flag1 <= '1';
else
flag1 <= '0';
end if;
end process;
process(cou2)
begin
if(cou2 = "01" ) then
flag2 <= '1';
else
flag2 <= '0';
end if;
end process;
flag <= flag1 or flag2;
end body_cout;