EEPW论坛

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY counter IS PORT ( DATAIN :IN integer range 0 to 15; CLK :IN std_logic; CLR :IN std_logic; LOAD :IN std_logic; DATAOUT :OUT integer range 0 to 15; CP :OUT std_logic); END counter; ARCHITECTURE behav OF counter IS SIGNAL num :integer range 0 to 15; SIGNAL CP0 :std_logic; BEGIN PROCESS(CLK,CLR) BEGIN IF ( CLR = '1' ) THEN num <= 0; ELSE IF ( CLK'event AND CLK = '1') THEN IF ( LOAD = '1') THEN num <= DATAIN; ELSE num <= num + 1; END IF; IF ( num = 15 ) THEN CP0 <= '1'; ELSE CP0 <= '0'; END IF; END IF; END IF; END PROCESS; DATAOUT <= num; CP <= CP0; END; --maxplus2下调试通过