EEPW论坛

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(cin:in std_logic; a,b:in std_logic_vector(3 downto 0); s:out std_logic_vector(3 downto 0); cout std_logic); end adder; architecture behav of adder is signal temp:std_logic_vector(4 downto 0); begin process(a,b,cin) begin temp<=('0'&a)+b+cin; if(temp(3 downto 0)>9 or (temp(4)='1')then s<=temp(3 downto 0)+6; co<='1'; else s<=temp(3 downto 0); co<='0'; end if; end process; end behav; unexpected end-of-file -try using the Text Editor's Syntax Coloring command to find the missing delimiter or keyword