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我编写的状态机，在功能仿真的时候可以完成我要的功能，可是为什么下到板子里功能就不对了，仿真和实际差在哪里呢
可是在下到板子后RD一直是高电平，没有出来上图的结果？
附代码；module ADCNT(D,Clk,Busy,
      ,RESET,CS,ConvSTX,RD,Lock0,Q,ret,flag);
input [15:0] D;
input Clk,Busy,ret;
output ConvSTX,RESET;
output RD,Lock0,CS,flag;
output [15:0] Q;
reg [15:0] REGL;
reg ConvSTX,RESET,flag;
wire CS;
wire [15:0] Q;
reg Lock,RD;
parameter st0=4'b0000,st1=4'b0001,st2=4'b0010,st3=4'b0011,st4=4'b0100,st5=4'b0101;
parameter st6=4'b0110,st7=4'b0111,st8=4'b1000,st9=4'b1001,st10=4'b1010,st11=4'b1011;
parameter st12=4'b1100,st13=4'b1101,st14=4'b1110,st15=4'b1111;
reg [3:0] current_states, next_states;
 assign CS= 0;
 assign Q= REGL;
 assign Lock0= Lock;

 always@(current_states)
  begin
      
      case(current_states)
   
    st0:begin
        RESET<=0;
         ConvSTX<= 0;
            Lock<=0;
            RD<=1;
            flag<=1;
            next_states<=st1;           
         end //Initial

    st1:begin
      RESET<=1;
     ConvSTX<= 1;
     Lock<= 0;
     RD<= 1;
      flag<=0;
     next_states<= st2;
    
          end //启动采样
    st2:begin
     RESET<=1;
     ConvSTX<= 1;
     Lock<= 0; 
     flag<=1;                                                                                   RD<= 1;
     if(Busy==0) 
      begin
        RD<=1;
       next_states<= st3;
     
      end
     else
      next_states<= st2;
        end //如果busy为0 转换结束 进入状态st3

    st3: begin
    RESET<=1;
    ConvSTX<= 1;
     Lock<= 1;
     RD=0;
     flag<=0;
     next_states<= st4; 
         end //第一路转换结果储存
 
  st4: begin
    RESET<=1;
    ConvSTX<= 1;
     Lock<= 0;
     RD=1;
     flag<=1;
      next_states<= st5;
        end //将RD拉高
  
  st5: begin
    RESET<=1;
    ConvSTX<= 1;
     Lock<= 1;
     RD=0;
     flag<=0;
      next_states<= st6;
     
         end //第二路转换结果储存
     st6: begin
     RESET<=1;
    ConvSTX<= 1;
     Lock<= 0;
      RD=1;
      flag<=1;
     next_states<= st7;
   
         end //将RD拉高 
     st7: begin
     RESET<=1;
   ConvSTX<= 1;
     Lock<= 1;
      RD=0;
      flag<=0;
     next_states<= st8;
   
         end //第三路转换结果储存
    st8: begin
    RESET<=1;
    ConvSTX<= 1;
     Lock<= 0;
     RD=1;
      flag<=1;
     next_states<= st9;
   
         end //将RD拉高
    st9: begin
    RESET<=1;
   ConvSTX<= 1;
     Lock<= 1;
     RD=0;
     flag<=0;
     next_states<= st10;
   
         end //第四路转换结果储存
     st10: begin
     RESET<=1;
     ConvSTX<= 1;
     Lock<= 0;
     RD=1;
     flag<=1;
     next_states<= st11;

         end //将RD拉高
    st11: begin
     RESET<=1;
     ConvSTX<= 1;
     Lock<= 1;
     RD=0;
     flag<=0;
     next_states<= st12;

         end //第五路转换结果储存
     st12: begin
     RESET<=1;
     ConvSTX<= 1;
     Lock<= 0;
     RD=1;
     flag<=1;
     next_states<= st13;

         end //将RD拉高
     st13: begin
     RESET<=1;
     ConvSTX<= 1;
     Lock<= 1;
     RD=0;
     flag<=0;
     next_states<= st14;

         end //第六路转换结果储存
     st14: begin
     RESET<=1;
       ConvSTX<= 1;
           Lock<=0;
           RD<=1;
           flag<=1;
           next_states<=st0;

           end
    default:begin
    RESET<=0;
      next_states<= st0;
     end
   endcase
  end

 
always@(posedge Clk)
 
  begin
   if(ret)
   //RESET<=0;
 
   current_states<= next_states;
 
else
    current_states<=st0;
    end
 
always@(posedge Lock)
  begin
   REGL <= D;
       
  end //如果lock上升沿来了 将AD7656输出的结果送给REGL
 endmodule


还请大家帮忙看看