OpenVINOTM,给你看得见的未来!>>
电子产品世界 » 论坛首页 » 企业专区 » Xilinx » 全自动洗衣机控制器

共4条 1/1 1 跳转至

全自动洗衣机控制器

菜鸟
2009-08-25 22:29:58    评分
简易的全自动洗衣机控制器

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity XiYiJi is

              port(

                     clk_50M        :in std_logic;

                     k_select :in std_logic;

                     k_run_stop     :in std_logic;

                     ---------------------------------------------

                     led_state  :out std_logic_vector(3 downto 0);---zhishi 11 ge zhuang tai

                     hex0              :out std_logic_vector(7 downto 0);

                     hex1              :out std_logic_vector(7 downto 0);

                     hex2              :out std_logic_vector(7 downto 0);

                     hex3              :out std_logic_vector(7 downto 0);

                     ---------------------------------------------

                     ctrl_danxi       :out std_logic;

                     ctrl_danpiao:out std_logic;

                     ctrl_dantuo :out std_logic);

end XiYiJi;

---------------------------------------------------------

architecture state_machine1 of XiYiJi is

type state_type is (s_wt_idle,s_wt_dx,s_wt_dp,s_wt_dt,s_wt_pt,s_wt_xpt,s_dx,s_dp,s_dt,s_pt,s_xpt);

signal present_state,next_state:state_type;

signal a1,a2,a3:integer range 0 to 9;

signal a4:integer range 0 to 9;

signal clk_10ms:std_logic;

signal clk_10ms_v:std_logic_vector(1 downto 0);

signal time_up : std_logic;

signal k1_v,k2_v:std_logic_vector( 5 downto  0  );

signal from_idle:std_logic;

signal state_unfinish:std_logic;

begin

---------------------------------------------------------

caiyang:process(clk_50M,k_select,k_run_stop)

       begin

              if rising_edge(clk_10ms) then

                     k1_v(5)<=k1_v(4);          --用于消抖

                     k1_v(4)<=k1_v(3);

                     k1_v(3)<=k1_v(2);

                     k1_v(2)<=k1_v(1);

                     k1_v(1)<=k1_v(0);

                     k1_v(0)<=k_select;

                     k2_v(5)<=k2_v(4);

                     k2_v(4)<=k2_v(3);

                     k2_v(3)<=k2_v(2);

                     k2_v(2)<=k2_v(1);

                     k2_v(1)<=k2_v(0);

                     k2_v(0)<=k_run_stop;

              end if ;                 

       end process;

----------------------------------------------------------------------------

state_transfer:process(clk_10ms,present_state,next_state,k1_v,k2_v)

       begin

              if rising_edge(clk_10ms)then

                     if present_state=s_wt_idle then

                            from_idle<='1';----zan ting hou  ji shi xian shi panduan

                            if k1_v ="00011"then

                                   next_state<=s_wt_dx;

                            end if ;

                     elsif present_state=s_wt_dx then                       

                            if k1_v="00011"then

                                   next_state<=s_wt_dp;

                            end if;

                            if k2_v="00011"then

                                   next_state<=s_dx;

                            end if ;

                     elsif present_state=s_wt_dp then

                            if k1_v="00011"then

                                   next_state<=s_wt_dt;

                            elsif k2_v="00011"then

                                          next_state<=s_dp;

                            end if ;

                     elsif present_state =s_wt_dt then

                            if k1_v="00011"then

                                   next_state<=s_wt_pt;

                            elsif k2_v="00011"then

                                   next_state<=s_dt;

                            end if ;   

                     elsif present_state=s_wt_pt then

                            if k1_v="00011"then

                                   next_state<=s_wt_xpt;

                            elsif k2_v="00011"then

                                   next_state<=s_pt;

                            end if ;

                     elsif present_state=s_wt_xpt then

                            if k1_v="00011"then

                                   next_state<=s_wt_idle;

                            elsif k2_v="00011"then

                                   next_state<=s_xpt;

                            end if ;

                     elsif present_state=s_dx then

                            from_idle<='0';

                            if time_up='1'then

                                   next_state<=s_wt_dx;

                                   state_unfinish <='0';            

                            end if;

                            if k2_v="00011" then

                                   next_state<=s_wt_dx;

                                   state_unfinish <='1';                          

                            end if ;

                     elsif present_state=s_dp then

                            from_idle<='0';

                            if time_up='1'then

                                   next_state<=s_wt_dp;

                                   state_unfinish <='0';     

                            end if;

                            if k2_v="00011"then

                                   next_state<=s_wt_dp;

                                   state_unfinish <='1';     

                            end if ;

                     elsif present_state=s_dt then

                            from_idle<='0';

                            if time_up='1'then

                                   next_state<=s_wt_dt;

                                   state_unfinish <='0';     

                            end if;

                            if k2_v="00011"then

                                   next_state<=s_wt_dt;

                                   state_unfinish <='1';     

                            end if ;

                     elsif present_state=s_pt then

                            from_idle<='0';

                            if time_up='1'then

                                   next_state<=s_wt_pt;

                                   state_unfinish <='0';     

                            end if;

                            if k2_v="00011"then

                                   next_state<=s_wt_pt;

                                   state_unfinish <='1';     

                            end if ;

                     elsif present_state=s_xpt then

                      from_idle<='0';

                            if time_up='1'then

                                   next_state<=s_wt_xpt;

                                   state_unfinish <='0';     

                            end if;

                            if k2_v="00011"then

                                   next_state<=s_wt_xpt;

                                   state_unfinish <='1';     

                            end if ;

                  end if;

 

              end if;

       end process;

-------------------------------------------------------------------

fenpin_1ms:process(clk_50M)

variable clk_div:integer range 0 to 25;--0000;

begin

       if rising_edge(clk_50M)then

              clk_div:=clk_div+1;

              if clk_div=25 then--0000

                     clk_10ms<=not clk_10ms;

                     clk_div:=0;

           end if;

        end if;

end process;

-------------------------------------------------------------------

caiyang1:process(clk_50M,clk_10ms)-----caiyang yongyi xiaochu shijian yanchi

       begin

              if rising_edge(clk_50M) then

                     clk_10ms_v(1)<=clk_10ms_v(0);

                     clk_10ms_v(0)<=clk_10ms;

              end if;

       end process;

-------------------------------------------------------------------

state_register:process(clk_50M)

       begin

              if rising_edge(clk_50M)then

                     present_state<=next_state;

              end if;

       end process;

--------------------------------------------------------------------

zhuangtaichuli:process(clk_50M,clk_10ms_v,present_state,time_up)

begin

       if rising_edge(clk_50M) then

                    

              case present_state is

                     when s_wt_idle =>

                           

                            a4<=8;a3<=8;a2<=8;a1<=8;

                            led_state <="1111";

                            ctrl_danxi<='0';---lv deng yun xing zhishi

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_wt_dx =>

--                   if state_unfinish='1'then

                            if from_idle='1'or time_up='1'then

                                   a4<=2;a3<=0;a2<=0;a1<=0;

                            end if ;

                            led_state <="0001";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_wt_dp =>

                            if from_idle='1'or time_up='1'then

                                   a4<=1;a3<=5;a2<=0;a1<=0;

                            end if;

                            led_state <="0010";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_wt_dt =>

                            if from_idle='1'or time_up='1'then

                                   a4<=1;a3<=0;a2<=0;a1<=0;

                            end if ;

                            led_state <="0011";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_wt_pt =>

                            if from_idle='1'or time_up='1'then

                                   a4<=3;a3<=5;a2<=0;a1<=0;

                            end if;

                            led_state <="0100";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_wt_xpt =>

                            if from_idle='1'or time_up='1'then

                                   a4<=4;a3<=5;a2<=0;a1<=0;

                            end if ;

                            led_state <="0101";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                     when s_dx =>                     

                            led_state <="0110";

                            ctrl_danxi<='1';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

                            if clk_10ms_v="01" then----------weihe jiu neng xiaochushijianyanchi

--                          if rising_edge(clk_10ms)then

                                   a1<=a1-1;

                                   if a1=0 then

                                          a2<=a2-1;a1<=9;

                                          if a2=0 then

                                                 a3<=a3-1;a2<=9;

                                                 if a3=0 then

                                                        a4<=a4-1;a3<=9;

                                                        if a4=0 and a3=0 and a2=0 and a1=0 then

                                                        time_up<='1';

                                                        a4<=0;a3<=0;a2<=0;a1<=0;

                                                        else time_up<='0';

                                                 end if;

                                          end if;

                                   end if;

                            end if;

                     end if;    

                  when s_dp =>                     

                            led_state <="0111";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='1';

                            ctrl_dantuo<='0';

                            if clk_10ms_v="01" then

--                          if rising_edge(clk_10ms)then

                                   a1<=a1-1;

                                   if a1=0 then

                                          a2<=a2-1;a1<=9;

                                          if a2=0 then

                                                 a3<=a3-1;a2<=9;

                                                 if a3=0 then

                                                        a4<=a4-1;a3<=9;

                                                        if a4=0 and a3=0 and a2=0 and a1=0 then

                                                        time_up<='1';

                                                        a4<=0;a3<=0;a2<=0;a1<=0;

                                                        else time_up<='0';

                                                 end if;

                                          end if;

                                   end if;

                            end if;

                     end if;    

                     when s_dt =>                     

                            led_state <="1000";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='1';

                            if clk_10ms_v="01" then

--                          if rising_edge(clk_10ms)then

                                   a1<=a1-1;

                                   if a1=0 then

                                          a2<=a2-1;a1<=9;

                                          if a2=0 then

                                                 a3<=a3-1;a2<=9;

                                                 if a3=0 then

                                                        a4<=a4-1;a3<=9;

                                                        if a4=0 and a3=0 and a2=0 and a1=0 then

                                                        time_up<='1';

                                                        a4<=0;a3<=0;a2<=0;a1<=0;

                                                        else time_up<='0';

                                                 end if;

                                          end if;

                                   end if;

                            end if;

                     end if;    

                     when s_pt =>                     

                            led_state <="1001";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='1';

                            ctrl_dantuo<='1';

                            if clk_10ms_v="01" then

--                          if rising_edge(clk_10ms)then

                                   a1<=a1-1;

                                   if a1=0 then

                                          a2<=a2-1;a1<=9;

                                          if a2=0 then

                                                 a3<=a3-1;a2<=9;

                                                 if a3=0 then

                                                        a4<=a4-1;a3<=9;

                                                        if a4=0 and a3=0 and a2=0 and a1=0 then

                                                        time_up<='1';

                                                        a4<=0;a3<=0;a2<=0;a1<=0;

                                                        else time_up<='0';

                                                 end if;

                                          end if;

                                   end if;

                            end if;

                     end if;    

                     when s_xpt =>                           

                            led_state <="1010";

                            ctrl_danxi<='1';

                            ctrl_danpiao<='1';

                            ctrl_dantuo<='1';

                            if clk_10ms_v="01" then

--                          if rising_edge(clk_10ms)then

                                   a1<=a1-1;

                                   if a1=0 then

                                          a2<=a2-1;a1<=9;

                                          if a2=0 then

                                                 a3<=a3-1;a2<=9;

                                                 if a3=0 then

                                                        a4<=a4-1;a3<=9;

                                                        if a4=0 and a3=0 and a2=0 and a1=0 then

                                                        time_up<='1';

                                                        a4<=0;a3<=0;a2<=0;a1<=0;

                                                        else time_up<='0';

                                                 end if;

                                          end if;

                                   end if;

                            end if;

                     end if;    

                     when others =>

                            a4<=8;a3<=8;a2<=8;a1<=8;

                            led_state <="1111";

                            ctrl_danxi<='0';

                            ctrl_danpiao<='0';

                            ctrl_dantuo<='0';

              end case;

       end if;

end process;

-------------------------------------------------------------------------

a1yimaxianshi:process(clk_50M,a1)

begin

       if rising_edge(clk_50M)then

              case a1 is

                     when 0=>

                     hex0<="11000000";

                     when 1=>

                     hex0<="11111001";

                     when 2=>

                     hex0<="10100100";

                     when 3=>

                     hex0<="10110000";

                     when 4=>

                     hex0<="10011001";

                     when 5=>

                     hex0<="10010010";

                     when 6=>

                     hex0<="10000010";

                     when 7=>

                     hex0<="11111000";

                     when 8=>

                     hex0<="10000000";

                     when others=>

                     hex0<="10010000";

              end case;       

       end if;

end process;

a2yimaxianshi:process(clk_50M,a2)

begin

       if rising_edge(clk_50M)then

              case a2 is

                     when 0=>

                     hex1<="11000000";

                     when 1=>

                     hex1<="11111001";

                     when 2=>

                     hex1<="10100100";

                     when 3=>

                     hex1<="10110000";

                     when 4=>

                     hex1<="10011001";

                     when 5=>

                     hex1<="10010010";

                     when 6=>

                     hex1<="10000010";

                     when 7=>

                     hex1<="11111000";

                     when 8=>

                     hex1<="10000000";

                     when others=>

                     hex1<="10010000";

              end case;       

       end if;

end process;

a3yimaxianshi:process(clk_50M,a3)

begin

       if rising_edge(clk_50M)then

              case a3 is

                     when 0=>

                     hex2<="11000000";

                     when 1=>

                     hex2<="11111001";

                     when 2=>

                     hex2<="10100100";

                     when 3=>

                     hex2<="10110000";

                     when 4=>

                     hex2<="10011001";

                     when 5=>

                     hex2<="10010010";

                     when 6=>

                     hex2<="10000010";

                     when 7=>

                     hex2<="11111000";

                     when 8=>

                     hex2<="10000000";

                     when others=>

                     hex2<="10010000";

              end case;       

       end if;

end process;

a4yimaxianshi:process(clk_50M,a4)

begin

       if rising_edge(clk_50M)then

              case a4 is

                     when 0=>

                     hex3<="11000000";

                     when 1=>

                     hex3<="11111001";

                     when 2=>

                     hex3<="10100100";

                     when 3=>

                     hex3<="10110000";

                     when 4=>

                     hex3<="10011001";

                     when 5=>

                     hex3<="10010010";

                     when 6=>

                     hex3<="10000010";

                     when 7=>

                     hex3<="11111000";

                     when 8=>

                     hex3<="10000000";

                     when others=>

                     hex3<="10010000";

              end case;       

       end if;

end process;

-------------------------------

end state_machine1;

 




关键词: 全自动     洗衣机     控制器     logic     state     d    

院士
2009-08-26 08:42:12    评分
2楼
全部的代码啊

院士
2009-08-26 08:42:24    评分
3楼
全部的代码啊

高工
2009-08-26 12:37:05    评分
4楼
对于状态机,只要能把状态理清楚,就容易了,能在纸上画出来,就能用代码写出来。

共4条 1/1 1 跳转至

回复

匿名不能发帖!请先 [ 登陆 注册 ]