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PETrainer ML, a Multi-Lane PCI Express™ (x1, x4) Exerciser, is a critical test and verification tool intended to assist you in improving the reliability of the solutions, while providing advanced capabilities for stress and compliance testing.

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T2-16 Analyzer is LeCroy’s fourth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 5 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications.

LeCroy’s PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.

Developers can use LeCroy’s PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.

LeCroy is well known for its technical leadership. Customers have come to depend on LeCroy supporting protocols while they are early in development when these tools are essential.

The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.

LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.

The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.

The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.

Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.

PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.

The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today’s internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.

PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.

The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.

The key features of PCI Express technology are:

• Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
• Advanced power management
• Compatible with existing PCI OS’s and software drivers
• Data integrity and error handling
• Support for real-time data traffic
• Support for multiple connection types such as chip-to-chip and board-to-board connectors

A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.

PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.

Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.

For more industry news and information on how to get in the "Express Lane", please visit the following:

• PCI-SIGhttp://www.pcisig.com/home
• Intel Developer Network for PCI

The Summit T2-16 Protocol Analyzer captures, decodes and displays PCIe 2.5GT/s and 5GT/s data rates for x1, x2, x4, x8, x16 lane widths

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T2-16 Analyzer is LeCroy’s fourth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 5 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications.

LeCroy’s PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.

Developers can use LeCroy’s PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.

LeCroy is well known for its technical leadership. Customers have come to depend on LeCroy supporting protocols while they are early in development when these tools are essential.

The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.

LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.

The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.

The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.

Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.

PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.

The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today’s internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.

PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.

The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.

The key features of PCI Express technology are:

• Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
• Advanced power management
• Compatible with existing PCI OS’s and software drivers
• Data integrity and error handling
• Support for real-time data traffic
• Support for multiple connection types such as chip-to-chip and board-to-board connectors

A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.

PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.

Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.

For more industry news and information on how to get in the "Express Lane", please visit the following:

• PCI-SIGhttp://www.pcisig.com/home
• Intel Developer Network for PCI

The PETracer product family includes a wide variety of Interposer systems, designed to reliably capture serial data traffic while minimizing perturbations in the serial data stream. Probes include interposers, which are designed to capture data traffic crossing the PCI Express card connector interface, and MidBus probes, which are designed to capture traffic flowing within a PCB.

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T2-16 Analyzer is LeCroy’s fourth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 5 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications.

LeCroy’s PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.

Developers can use LeCroy’s PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.

LeCroy is well known for its technical leadership. Customers have come to depend on LeCroy supporting protocols while they are early in development when these tools are essential.

The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.

LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.

The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.

The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.

Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.

PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.

The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today’s internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.

PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.

The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.

The key features of PCI Express technology are:

• Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
• Advanced power management
• Compatible with existing PCI OS’s and software drivers
• Data integrity and error handling
• Support for real-time data traffic
• Support for multiple connection types such as chip-to-chip and board-to-board connectors

A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.

PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.

Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.

For more industry news and information on how to get in the "Express Lane", please visit the following:

• PCI-SIGhttp://www.pcisig.com/home
• Intel Developer Network for PCI

The Summit T3-16 Protocol Analyzer captures, decodes and displays PCIe 3.0 protocol traffic.data rates for x1, x2, x4, x8, x16 lane widths

LeCroy offers three protocol analyzer product lines (Summit™ , PETracer™ ML, Edge T1-4). The Summit T2-16 Analyzer is LeCroy’s fourth generation architecture and highest performance platform. It provides full bidirectional support of x16, x8, x4, x2, and x1 at data rates up to 5 GT/s.With 8 GB of trace memory, it offers enough capacity for analyzing and recording extensive PCI Express data streams. Supporting lane widths up to x4 at 2.5 GT/s, the PETracer ML Analyzer has 2 GB of trace memory and offers outstanding performance for Gen1 PCI Express applications. For portability and ease-of-use the Edge T1-4 Analyzer offers Gen1 analysis and low cost form factor for add-in-boards applications.

LeCroy’s PCI Express Protocol Analyzer solutions employ high impedance, non-intrusive probing technology thereby allowing fully unaltered data pass-through. In addition, it leverages the intuitive and powerful LeCroy Trace expert software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies and presents this knowledge to the user in a colorful, intuitive and easy to use graphical display, allowing users to quickly capture and validate PCI Express product designs. These analyzers enable IP, semiconductor, switch, software and system developers as well as add-on card vendors to quickly identify protocol violations and ultimately reduce development and debugging time.

Developers can use LeCroy’s PCI Express Protocol solutions to easily capture and decode PCI Express Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs), and low-level link traffic, including Training Sequences and Skip Ordered-sets. Some of the errors detected include: 8b/10b errors, such as invalid symbols and incorrect running disparity; CRC errors; idle data errors; and EDB (End-of-Packet Bad) errors. They also provide a detailed display of split transactions, correlating requests transmitted from one PCI Express endpoint with completions received from the endpoint at the opposite end of the link.

LeCroy is well known for its technical leadership. Customers have come to depend on LeCroy supporting protocols while they are early in development when these tools are essential.

The PCI Express exercisers assist with generating PCI Express transactions, observing behavior, and performing both stress testing and compliance testing. The Summit Z3-16 supports the new Specification 3.0 ("Gen3") data rates of 8 GT/s across up to 16 lanes. The PETrainer ML Exerciser supports up to x4 lane widths at data rates of 2.5 GT/s. As complete solutions, both the Summit T3-16 and Summit Z3-16, or PETracer/Trainer™ systems give you the unique ability to record (capture) live traffic, modify the traffic, and then playback the exact data stream, or "script," using the exerciser.

LeCroy offers an integrated and automated compliance testing system, including the Protocol Test Card, approved by the PCI-SIG® as a standard tool for compliance testing for developers working with the new Gen2 specification.

The LeCroy SDA 6020 Analyzer and PCI Express Compliance and Development software offer a complete test and debug. QPHY-PCIe provides a highly automated solution for PCI Express 1.1.

The LeCroy SDA 13000 can perform PCI Express 2.0 Compliance Test and Debug. It can acquire and quickly analyze PCI Express 2.0 signals using the SigTest(PCI-SIG Compliance Utility). The SDA 13000 has the memory depth to acquire all required 1 million UI in a single acquisition. Waveforms can be saved in the TRC format and quickly analyzed by SigTest. Built into the standard SDA tools are the 14 Masks, 3 PLLs and 2 Jitter Filters specified by PCI-SIG.

Peripheral Component Interconnect Express(PCIe) protocol was developed by Microsoft, Dell, IBM, Intel, and others in 2002. It was first called 3GIO but later became known as PCI Express. The PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8V, 2.5GT/s(Giga Transfers), to the newly announced Gen3 at 8GT/s the PCI Express technology roadmap will continue to evolve, while maintaining backward compatibility, well into the next decade with enhancements to its protocol, signaling, electromechanical and other specifications. The PCI Express architecture retains the PCI usage model and software interfaces for investment protection and smooth development migration. The technology is aimed at multiple market segments in the computing and communication industries, and supports chip-to-chip, board-to-board and adapter solutions at an equivalent or lower cost structure than existing PCI designs. PCI Express 2.0 currently runs at 5GT/s or 500MBps per lane in each direction, providing a total bandwidth of 16GBps in a 16-lane configuration which is the largest size in use.

PCI Express Gen3 will run at 8GT/s but will use a different encoding system to double the data rate but keep power consumption as low as possible.

The PCI bus is aging. Continued emergence of faster CPU and memory speeds, high-performance graphics, gigabit networking and other applications requiring higher bandwidth have made this once proud I/O the bottleneck. PCI simply cannot keep up with these faster applications. In addition, today’s internal systems are composed of numerous and sometimes proprietary interconnects, thus making it difficult for multiple internal and external systems to have a unified I/O.

PCI Express is ready to meet the challenges of new and emerging applications for the next decade. It is designed to tie together many different chip-level I/O components within PC systems and to partition the system by providing very high-speed interconnections between different functional units - which will enable radical new designs.

The PCI Express architecture is a general-purpose I/O interconnect that can scale across multiple market segments in both the computing and communications industries. It is designed to provide connectivity as a chip-to-chip interconnect, I/O interconnect for adapter cards, an I/O attach point to other interconnects such as 1394b, USB2.0, InfiniBand and Ethernet and as a graphics I/O attach point for increased graphics bandwidth.

The key features of PCI Express technology are:

• Scalable performance, achieved through wider link widths (x1, x2, x4, x8, x16, x32)
• Advanced power management
• Compatible with existing PCI OS’s and software drivers
• Data integrity and error handling
• Support for real-time data traffic
• Support for multiple connection types such as chip-to-chip and board-to-board connectors

A PCI Express Link is composed of two low-voltage differential pairs; a dual simplex connection between A and B devices. Data transmission between A and B are run simultaneously in both directions. Links cannot be configured asymmetrically, with more lanes in one direction versus the other.

PCI Express is intended to support multiple connection types, including chip-to-chip connectors on a system board; board-to-board connectors such as PCI add-in card interconnects today; docking stations for mobile platforms; as well as new form factors yet to be developed. This flexibility will allow for innovative and radical designs in platforms for years to come.

Using a PCIE Protocol Analyzer from LeCroy allows developers to see PCIe transactions from the low level wire up through to the upper PCIe protocol layers. From this diagram a bit stream is extracted to a packet. Packets are extracted into one or more transactions. Transactions may be further integrated into higher level transfers. Looking at data this way allows better understanding of how well the protocol has been implemented and is performing.

For more industry news and information on how to get in the "Express Lane", please visit the following:

• PCI-SIGhttp://www.pcisig.com/home
• Intel Developer Network for PCI

The LeCroy QPHY-PCIe Test Solution provides automated control for LeCroy oscilloscopes for performing the entire transmitter physical layer tests as described by the Card Electro-mechanical specification Rev 1.1 and 2.0 

• Compliant with the Card Electro-mechanical Specification Rev 1.1 and 2.0
• Support for system and add-in card testing
• Integrated SigTest libraries into the oscilloscope software enables automation of the exact algorithms used for compliance testing
• Connection diagrams display proper setup using the PCI-SIG Compliance Base Boards and Compliance Load Boards.
• Report generation incorporates CEM test assertions for 2.5Gb/s, 5.0Gb/s with 3.5dB of de-emphasis and 5.0Gb/s with 6.0 dB of de-emphasis
• Simple and easy-to-use automated testing

The LeCroy QPHY-PCIe Test Solution provides automated control for LeCroy oscilloscopes for performing the entire transmitter physical layer tests as described by the Card Electro-mechanical specification Rev 1.1 and 2.0

Testing requirements for both system boards and add-in cards are described by the specification. QPHY-PCIe has the ability to test compliance in accordance with the specification for both system boards and add-in cards.

By integrating the SigTest libraries into the oscilloscope software, QPHY-PCIe can fully automate all of the required compliance tests using the exact same algorithms that are described by the specification.

Additionally, QPHY-PCIe can run all of the 2.5GT/s tests, then all of the 5.0GT/s with 3.5dB of de-emphasis test, and finally all of the 5.0Gt/s with 6.0dB of de-emphasis tests. This allows the user to create one test report for all 3 testing phases.

These capabilities make QPHY-PCIe an all-inclusive automated test suite that meets the requirements for 2.5GT/s and 5.0GT/s PCI Express transmitter compliance testing.

By integrating the SigTest libraries into the oscilloscope software, the exact algorithms provided by the PCI-SIG are used for calculating the results. This ensure the same exact answer as running the stand alone SigTest utility with the added benefit of being able to run this utility from within the oscilloscope software.

Measurement results often need to be summarized and tabulated to quickly verify specifications. This information, together with instrument and signal acquisition/test condition setups, results in a fully documented record. QPHY-PCIe streamlines this process by incorporating an automatic HTML report generation engine. The created test reports contain tabulated numerical values for each individual test result, including PASS/FAIL and specification limit columns. Reports can also be saved as PDF, HTML or XML.

If a compliance failure is found, LeCroy's SDA II serial data analysis package is available to help find the root cause quickly and easily. SDA II has the ability to perform Eye and Jitter measurements simultaneously and is fully integrated into the oscilloscope application software. In addition, with specialized features such as IsoBER, ISI Plot, Pj Inverse FFT and multiple jitter models, SDA II provides insight into the measured Eye and Jitter parameters making it easier to identify the sources of problems.

The Eye Doctor II analysis software allows the user to view their signal after Continuous Time Linear Equalization (CTLE), Feed Forward Equalization (FFE) and/or Decision Feedback Equalization (DFE). This gives the user to ability to see how an actual receiver that utilizes equalization would interpret their signal.

LeCroy's SDA II analysis software contains integrated jitter and timing analysis for clock and data signals. It allows analysis of data up to the memory limit of the oscilloscope and using X-Stream II technology, SDA II can display eye diagrams and jitter decomposition results up to 50 times faster than other solutions. Additionally, the specific PLL for PCI Express is selectable from a list of pre-configured PLLs. Lastly, SDA II contains 2 separate methods for jitter decomposition; the industry standard spectral method, and the NQ-scale methods. NQ-scale is critical for properly distinguishing between random and deterministic jitter in systems where cross-talk is present.

Additionally, the Eye Doctor II analysis software also enables channel emulation. For PCIe testing, a design engineer will perform their serial data measurement at the output of the transmitter. However, analysis at the far side of a reference serial data channel is very useful for debugging problems.. To accomplish this they could either use a physical channel to make their measurement after the channel or they can use channel emulation to see what their serial data signal would look like if it had been transmitted through the channel.

The ProtoSync option further leverages the supported LeCroy decode annotation options (PCIEbus D, USB2bus D, USB3bus D, SASbus D, SATAbus D, and Fcbus D) installed on the oscilloscope.

ProtoSync is an option for LeCroy oscilloscopes that provides simultaneous views as follows:

1. Physical layer waveforms (captured by a LeCroy oscilloscope)
2. Decode annotation overlays (displayed on a LeCroy oscilloscope)
3. Protocol analysis views (displayed in a separate software window)

The ProtoSync option further leverages the supported LeCroy decode annotation options (PCIEbus D, USB2bus D, USB3bus D, SASbus D, SATAbus D, and Fcbus D) installed on the oscilloscope. It provides the ability to export the physical layer waveform data to a separate LeCroy protocol analysis software package (the same package that provides protocol analysis views when used with a LeCroy hardware protocol analyzer), and it synchronizes the data displays between the oscilloscope and protocol analysis software package. Selecting a specific portion of the decode annotated physical layer waveform on the oscilloscope will automatically select the corresponding protocol analysis software packet display, or vice-a-versa. Thus, debug and analysis using a variety of views is very easy.

ProtoSync is especially useful for standards that support dynamic equalization (PCI Express Gen3, and forthcoming versions of SAS). Dynamic equalization is a link initialization process where training sequences communicate transmitter and receiver parameters to establish a link. In the pre-silicon stage of development, protocol analyzer hardware may not yet be available or physical layer problems may be so prevalent that a protocol analyzer may not be able to provide the desired analysis. Yet debugging dynamic equalization is usually much easier if both analog waveforms and high level protocol packet data are available and are synchronized together so as to navigate to hard-to-find details of dynamic equalization.

In addition, more mature standards (PCI Express Gen1, SATA 1.5 Gb/s, etc.) are increasingly becoming embedded in system designs. Embedded systems usually present complex attachment or probing challenges that make it difficult to conveniently connect a protocol analyzer, or the embedded system engineer may not be familiar with the protocol analyzer tool. However, the challenges around connecting an oscilloscope to the embedded system are usually already known and resolved, and the debug and validation system engineer is quite familiar with the operation of an oscilloscope. By providing the ability to view advanced protocol packet data using physical layer oscilloscope captures as a source, complex problems can be more easily debugged.

ProtoSync runs on LeCroy WaveRunner, WavePro, and WaveMaster platforms.

LeCroy QPHY-PCIe3 Test Solution provides automated control for LeCroy oscilloscopes for performing transmitter physical layer tests as described by the PCI Express Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7.

• Compliant with the PCI Express® Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7
• Provides early debugging ability even though the compliance specification is not yet released
• Powerful SDA II analysis package helps to find the root cause of failures
• Eye Doctor II provides the ability to emulate and de-embed serial data channels and emulate receive equalizers for accurate testing
• QualiPHY automated test framework provides connection diagrams, automated oscilloscope operation and report generation

Although the PCI Express Compliance Specification is not yet released, the LeCroy QPHY-PCIe3 Test Solution provides automated control for LeCroy oscilloscopes for performing transmitter physical layer tests as described by the PCI Express Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7. This allows for early debugging of PCI Express 3.0 products early in preparation for compliance testing in the near future.

If a failure is found, LeCroy's SDA II serial data analysis package is available to help find the root cause quickly and easily. SDA II has the ability to perform Eye and Jitter measurements simultaneously and is fully integrated into the oscilloscope application software. In addition, SDA II provides insight into the measured Eye and Jitter parameters making it easier to identify the sources of problems.

Additionally, Eye Doctor II provides the channel emulation, de-embedding and equalization tools that engineers need for next generation serial data standards.

The LeCroy QualiPHY platform provides an easy to configure user interface, allows for custom test and limit selection, displays connection diagrams to the user to ensure proper connectivity, and generates a comprehensive test report. In addition, all of the waveforms tested by QPHY-PCIe3 can be saved to easily share information or rerun the tests at a later time.

• Vtx-fs-no-eq
• Vtx-EIEOS-FS Limits
• Vtx-EIEOS-RS Limits
• Compliance Eye Diagrams
• TTx-DDJ
• TTx-UTJ
• TTx-UDJDD
• TTX-UPW-TJ
• TTx-UPW-DJDD
• Unit Interval
• Vtx-cm-ac-pp
• Vtx-dc-cm