这些小活动你都参加了吗?快来围观一下吧!>>
电子产品世界 » 论坛首页 » 嵌入式开发 » MCU » 嵌入式系统初学者入门FAQ

共4条 1/1 1 跳转至

嵌入式系统初学者入门FAQ

工程师
2002-11-07 18:08:24     打赏
Q:什么叫做嵌入式系统? A:嵌入式系统被定义为:以应用为中心、以计算机技术为基础、软件硬件可裁剪、适应应用系统对功能、可靠性、成本、体积、功耗严格要求的专用计算机系统。嵌入式计算机在应用数量上远远超过了各种通用计算机,一台通用计算机的外部设备中就包含了5-10个嵌入式微处理器,键盘、鼠标、软驱、硬盘、显示卡、显示器、Modem、网卡、声卡、打印机、扫描仪、数字相机、USB集线器等均是由嵌入式处理器控制的。在制造工业、过程控制、通讯、仪器、仪表、汽车、船舶、航空、航天、军事装备、消费类产品等方面均是嵌入式计算机的应用领域。 嵌入式系统是将先进的计算机技术、半导体技术和电子技术和各个行业的具体应用相结合后的产物,这一点就决定了它必然是一个技术密集、资金密集、高度分散、不断创新的知识集成系统。嵌入式系统工业的基础是以应用为中心的"芯片"设计和面向应用的软件产品开发。(by xiaohua) Q:1、象CE或Vxworks这种系统我什么时候要用它?比如说51单片机的开发,椐我所知的是过程是这样的:比如说控制一组LED,先从硬件下手,做一块包含单片机及相关驱动的电路板,然后用C呀汇编编写程序,然后仿真烧写,结束。 在这个过程中没有用到操作系统,是不是也可以用到? 2、用这种系统开发一个产品时是否也需要自己做硬件,还是一般来讲有现成的可供使用的硬件?象PC一样? 3、如果有一天我需要做这方面的工作,我应该做哪些准备,比如说要买些什么工具等? A: 1.当然可以用到OS。 2。你可以购买开发板,或自己作。 3。首先你得有一个IDE环境,比如tornado等等。用它们编译生成的映象文件已经嵌入了OS内核。其次你得有开发板(目标机),当然PC(宿主机)是必不可少的。最后要常上网请教高手。(by seasoblue) Q: 对于你的回答我的理解是这样的,你看对吗? 让我感觉到这个过程与单片机的开发过程差不太多。比如说有这样一个任务:一个电梯控制统,它除了完成常规电梯的控制功能(例如电机的起停,安钮召唤等) 外,还可以通过网络传递一些信息。 第一我要选择一个我采用的OS支持的处理器。顺便问一句,象vxwords支持吗51吗? 然后选择一些I/O驱之类的芯片,做好PCB 第三找一个IDE的环境,我的理解是我买的OS带给我的。写程序,并且可仿真 写好通过后编译产生一个BIN或HEX文件,用烧写器把它写到ROM里就完了? 一个问题是:我的OS是一同烧进去的还是我要先做些什么事,再烧我的BIN? A: 你的理解基本正确。采用rtos的最大一个好处就是可以实现实时多任务。当然有些嵌入式OS的实时性并不好,比如由LINUX演变而来的几种嵌入式OS版本。  据我所知vxworks目前还没有针对51的bsp,因为51资源太少啦,上面跑vxworks不大现实。  OS是和应用程序一起烧进去的。(by seasoblue) 还望各位斑竹、网友多多补充!呵呵:) [align=right][color=#000066][此贴子已经被作者于2002-11-7 10:30:02编辑过][/color][/align]



关键词: 嵌入式     系统     初学者     入门    

工程师
2002-11-07 18:39:00     打赏
2楼
Introduction to JTAG Surface-mount technology rang the death knell for bed-of-nails testing. That's why a consortium of companies called the Joint Test Access Group came together to define a standard for boundary-scan testing of ICs and boards. Here's a primer on the technology. One disadvantage of shrinking technology is that the testing of small devices gets exponentially more complex. When circuit boards were large, we tested them with techniques such as bed-of-nails, which employed small spring-loaded test probes to make connections with solder pads on the bottom of the board. Such test fixtures were custom made, expensive, and inefficient, and much of the testing could not be performed until the design was complete. The problems with bed-of-nails testing were exacerbated as board dimensions got smaller and surface-mount packaging technology improved. If devices were mounted on both sides of a circuit board, no attachment points were left for the test equipment. Boundary scan To find a solution to these problems, a group of European electronics companies formed a consortium in 1985 called the Joint Test Action Group (JTAG). The consortium devised a specification for performing boundary-scan hardware testing at the IC level. In 1990, that specification resulted in IEEE 1149.1, a standard that established the details of access to any chip with a so-called JTAG port. The specification JTAG devised uses boundary-scan technology, which enables engineers to perform extensive debugging and diagnostics on a system through a small number of dedicated test pins. Signals are scanned into and out of the I/O cells of a device serially to control its inputs and test the outputs under various conditions. Today, boundary-scan technology is probably the most popular and widely used design-for-test technique in the industry. Test pins Devices communicate to the world via a set of I/O pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a dedicated path around the device's boundary (hence the name), as shown in Figure 1. The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs. [upload=gif]uploadImages/20021171039827515.gif[/upload] Figure 1: An integrated circuit with boundary scan During testing, I/O signals enter and leave the chip through the boundary-scan cells. The boundary-scan cells can be configured to support external testing for interconnection between chips or internal testing for logic within the chip. To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level. Test Access Port The boundary-scan control signals, collectively referred to as the Test Access Port (TAP), define a serial protocol for scan-based devices. There are five pins: TCK/clock synchronizes the internal state machine operations. TMS/mode select is sampled at the rising edge of TCK to determine the next state. TDI/data in is sampled at the rising edge of TCK and shifted into the device's test or programming logic when the internal state machine is in the correct state. TDO/data out represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state. TRST/reset (optional), when driven low, resets the internal state machine. The TCK, TMS, and TRST input pins drive a 16-state TAP controller state machine. The TAP controller manages the exchange of data and instructions. The controller advances to the next state based on the value of the TMS signal at each rising edge of TCK. With the proper wiring, you can test multiple ICs or boards simultaneously. An external file, known as a Boundary-Scan Description Language (BSDL) file, defines the capabilities of any single device's boundary-scan logic. Test process The standard test process for verifying a device or circuit board using boundary-scan technology is as follows: The tester applies test or diagnostic data on the input pins of the device. The boundary-scan cells capture the data in the boundary scan registers monitoring the input pins. Data is scanned out of the device via the TDO pin, for verification. Data can then be scanned into the device via the TDI pin. The tester can then verify data on the output pins of the device. Simple tests can find manufacturing defects such as unconnected pins, a missing device, an incorrect or rotated device on a circuit board, and even a failed or dead device. The primary advantage of boundary-scan technology is the ability to observe data at the device inputs and control the data at the outputs independently of the application logic. Another benefit is the ability to reduce the number of overall test points required for device access. With boundary scan there are no physical test points. This can help lower board fabrication costs and increase package density. Boundary scan provides a better set of diagnostics than other test techniques. Conventional techniques apply test vectors (patterns) to the inputs of the device and monitor the outputs. If there is a problem with the test, it can be time consuming to isolate the problem. Additional tests have to be run to isolate the failure. With boundary scan, the boundary-scan cells observe device responses by monitoring the input pins of the device. This enables easy isolation of various classes of test failures, such as a pin not making contact with the circuit board. Boundary scan can be used for functional testing and debugging at various levels, from internal IC tests to board-level tests. The technology is even useful for hardware/software integration testing. Debug Some test equipment and ASIC-cell companies have defined proprietary extensions that use the JTAG capability to implement software debug functions. With the proper support built into a target CPU, you can use this interface to download code, execute it, and examine register and memory values. These functions cover the majority of the low-level functionality of a typical debugger. An inexpensive remote debugger can be run on a workstation or PC to assist with software debug. Boundary-scan technology is also used for emulation. The emulator front-end acts as the scan manager by controlling the delivery of scan information to and from the target and the debugger window. (Of course, when a host controls the JTAG scan information, it needs to know if other devices are connected in the scan chain.) JTAG also allows the internal components of the device (the CPU, for example) to be scanned. This means you can use JTAG to debug embedded devices by allowing access to any part of the device that is accessible via the CPU, and still test at full speed. This has since become a standard emulation debug method used by silicon vendors. JTAG can also provide system level debug capability. Having extra pins on a device provides additional system integration capabilities for benchmarking, profiling, and system level breakpoints. As an engineering manager at Texas Instruments, Rob Oshana manages DSP and ARM code generation and build technologies, as well as DSP emulation technology. Contact him at roshana@ti.com.

菜鸟
2002-11-08 23:05:00     打赏
3楼
高兄, 最近辛苦拉, 没帮什么忙, sorry!

工程师
2003-01-28 17:44:00     打赏
4楼
是ftp.edw.com.cn U:gao P:123456789

共4条 1/1 1 跳转至

回复

匿名不能发帖!请先 [ 登陆 注册 ]