In today's designs it is typical to have a large number of clocks that interact with each other. In order to ensure that Vivado optimizes paths that are critical, it is essential to understand how the clocks interact and how they are related – synchronous and asynchronous clocks.
Synchronous clocks are clocks that are related to each other. For example, generated clocks from an MMCM or PLL are typically synchronous clocks provided the two clocks have a common period. If the clocks from the output of MMCM or PLL do not have a common period, then it is recommended to treat these clocks as asynchronous with proper synchronization techniques. You can easily identify clocks that are synchronous by running the report_clock_interaction report and then looking at the “Path Req (WNS)”, the “Clock Pair Classification” and the “Inter-Clock Constraints” columns. Here are three scenarios where you would treat clocks relationships as asynchronous and apply appropriate timing constraints:
If the clock interaction report has many (or even one) Red "Timed (unsafe)" and/or Orange "Partial False Path (unsafe)" rectangles then you have not constrained asynchronous clocks correctly. If your design has a number of asynchronous clock crossing domains, then you need to constrain those clock interactions.
Look at the "Clock Pair Classification" and "Inter-Clock Constraints" columns in the Report Clock Interactions reports. If the clock pair classification is "No Common Clock" or "No Common Period" and/or the Inter-clock Constraints says "Timed (unsafe)" then treat the interactions as asynchronous.
If the “Path Requirement (WNS)” column is very tight, typically less than 1 ns, or the “Inter-Clock Constraints” is Timed “Unsafe” or “Partial False Path (unsafe)” then it is recommended that you treat the clock interaction as asynchronous.
If the “WNS Path Requirement (ns)” is reasonable (>1 ns) and the "Inter-Clock Constraints is "Timed" and the “Clock Pair Classification” is “clean” then the clock interaction can be treated as synchronous meaning you don't need to add any timing constraints. The timer has automatically timed these paths as synchronous.
In order to constrain asynchronous clock domain crossings correctly, there are four things to consider:
If there are no paths between the two clocks, the simply use set_clock_groups or set_false_path between the two clocks.
If the paths are all single big CDCs then you can use set_clock_groups or set_false_path between the two clocks.
If the paths are all multi-bit paths, and you are concerned about the latency and the skew in the data bits, then use set_max_delay –datapath_only and the set_bus_skew constraint.
If there are a mix of single bit and multi-bit CDCs between two clocks then use explicit path-to-path false path constraints for the single bit CDCs and for the multi-bit CDCs use set_max_delay –datapath_only and set_bus_skew constraints.
If the clocks are synchronous, there is no need for any constraints. The STA engine in Vivado will automatically time the paths.