module jiafa
(
CLK,
RSTn,
data_out
);
input CLK;
input RSTn;
output [7:0] data_out;
reg rden;
reg [7:0] addr;
jiafa_2 U1
(
.clock(CLK),
.address(addr),
.rden(rden),
.q(data_out)
);
always @( posedge CLK or negedge RSTn)
if(!RSTn)
begin
rden <= 1'b0;
addr <= 8'd0;
end
else if(addr == 8'd32)
begin
rden <= 1'b0;
addr <= 8'd0;
end
else
begin
addr <= addr + 1'b1;
rden <= 1'b1;
end
endmodule