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是的啊，a是清零信号，但是仅仅在a上升沿将计数器清零。谢谢jason zhang的支持，你的资料很好，我看了很多

好的。下面是我的程序，红色部分是增加的东西，增加了后就通过不了综合了。综合的问题是在第二个always上面涂红，问题是the logic for gpshighclkcnt [15：0] does  not match a standard flip-flop.
module fuzhugen(gps,
                gpshighclk,
                rst,
                fuzhu,
                fuzhu1);      

input  gps;
input  gpshighclk;
input  rst;
output fuzhu;                      //增加一个fuzhu输出端口信号
output fuzhu1;                  //增加一个fuzhu1输出端口信号

reg        fuzhu;
reg        fuzhu1;
reg        lockgpshigh;
reg [15:0] gpshighclkcnt;

always @ (posedge gps or posedge gpshighclk)
begin
    if(rst)
        begin           
            gpshighclkcnt<=16'd0;
            fuzhu1<=(1==0);
            fuzhu<=(0==1);
        end
    else
        begin
            if(gps && !lockgpshigh)
                begin
                    gpshighclkcnt<=16'd0;
                    fuzhu<=(0==1); 
                    fuzhu1<=(0==1);                 
                end                 //gps信号上升沿时候，计数器清零，fuzhu和fuzhu1输出port清零

            if(gps && gpshighclkcnt==16'd239)
                begin
                    fuzhu <=(1==1);
                end            //当gps信号为高时并且计数器计数到239的时候fuzhu信号输出高电平

            if(gps && gpshighclkcnt==16'd240)
                begin
                    fuzhu1<=(1==1);                
                end          //当gps信号为高时并且计数器计数到240的时候fuzhu1信号输出高电平

            else
                begin
                    gpshighclkcnt<=gpshighclkcnt+16'd1;               
                end
        end
end

always @ (posedge gps or posedge gpshighclk)
begin
    if(rst)
        begin
            gpshighclkcnt<=16'd0;           
        end
    else
        begin
            if(gps && !lockgpshigh)
                begin
                    lockgpshigh<=(1==1);
                end
            else
                begin
                    if(!gps)
                        begin
                            lockgpshigh<=(1==0);
                        end
                end
        end
end

endmodule