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Verilog HDL: Creating a Hierarchical Design

This example describes how to create a hierarchical design using Verilog HDL. 
The file top_ver.v is the top level, which calls the two lower level files bottom1.v and bottom2.v.
download from: http://www.fpga.com.cn 


vprim.v 



top_ver.v 

module top_ver (q, p, r, out);

input     q, p, r;
output     out;
reg     out, intsig;

bottom1 u1(.a(q), .b(p), .c(intsig));
bottom2 u2(.l(intsig), .m(r), .n(out));

endmodule


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bottom1.v 

module bottom1(a, b, c);

input     a, b;
output     c;
reg      c;

always
begin
     c<=a & b;
end

endmodule


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bottom2.v 

module bottom2(l, m, n);

input     l, m;
output    n;
reg       n;

always
begin
     n<=l | m;
end
endmodule