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【应用手册】Implementing Loopback in Triple-Speed Ethernet Designs With LVDS I/O and GX Transceivers
This application note describes two reference designs that demonstrate various types
of loopback in a fully operational subsystem. The reference designs are SOPC Builder
systems that integrate multiple instances of the Triple-Speed Ethernet MegaCore®
functions operating in full-duplex mode with optional loopback paths.
One reference design runs in the Arria® II GX FPGA development board and
integrates instances of the Triple-Speed Ethernet IP core with embedded GX blocks.
The other reference design runs in the Stratix® IV FPGA development board and
integrates instances of the Triple-Speed Ethernet IP core with embedded LVDS IO
blocks.an633.pdf