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The Virtex®-II FPGA series provides dedicated on-chip blocks of 18 Kbit True Dual-Port synchronous RAM for use in FIFO applications. This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 511 to 36 FIFO, with the depth and width being adjustable within the Verilog or VHDL code. This document is obsolete/under obsolescence.

xapp258.pdf