EEPW论坛

5、按键防抖控制LED
（这个只是个实例，效果不是很好，改进的请进http://forum.eepw.com.cn/thread/221172/15#147）

按键S1、S2、S3、S4，控制电平翻转进而控制LED1、LED2、LED3、LED4的亮灭，按键S8为复位键。


module key_debounce(rst_n,clk,keyin,ledout);

 input rst_n;
 input clk;
 input[3:0] keyin;

 output[3:0] ledout;
 
 reg[19:0] cnt;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   cnt <= 20'd0;
  else
   cnt <= cnt + 1'b1;
 end
 
 wire sample_pulse = cnt == 20'hF4240;

 
 wire led0_out;
 key0 U1
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[0]),
  .ledout(led0_out)
 );
 
 wire led1_out;
 key1 U2
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[1]),
  .ledout(led1_out)
 );
 
 wire led2_out;

 key2 U3
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[2]),
  .ledout(led2_out)
 );
 
 wire led3_out;
 key3 U4
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[3]),
  .ledout(led3_out)
 );
 
 assign ledout = {led3_out,led2_out,led1_out,led0_out};

endmodule

//-----------------------key0----------------------- 
module key0(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 
 reg low_sw_r;
 
 always @(posedge clk )
  low_sw_r <= low_sw;
  
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end 

 assign ledout = ledout_r;
 
endmodule

//-----------------------key1----------------------- 
module key1(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk )
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
  
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;

 end 

 assign ledout = ledout_r;
 
endmodule

//-----------------------key2----------------------- 
module key2(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
  
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end 

 assign ledout = ledout_r;
 
endmodule

//-----------------------key3----------------------- 
module key3(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
  
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end 

 assign ledout = ledout_r;
 
endmodule

我也是新手，以后大家多讨论讨论

刚刚看见了，我就给你传