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别人的源码：
module my_led(rst_n,clk,keyin,ledout);

 input rst_n;
 input clk;
 input[3:0] keyin;

 output[3:0] ledout;
 
 reg[19:0] cnt;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   cnt <= 20'd0;//
  else
   cnt <= cnt + 1'b1;
 end
 
 wire sample_pulse = cnt == 20'hF4240;

 
 wire led0_out;
 
 key0 U1
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[0]),
  .ledout(led0_out)
 );//一个API的调用写了多行

  wire led1_out;
 key1 U2
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[1]),
  .ledout(led1_out)
 );
 
 wire led2_out;

 key2 U3
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[2]),
  .ledout(led2_out)
 );
 
 wire led3_out;
 key3 U4
 (
  .en(sample_pulse),
  .rst_n(rst_n),
  .clk(clk),
  .key(keyin[3]),
  .ledout(led3_out)
 );
 
 assign ledout = {led3_out,led2_out,led1_out,led0_out};//ledout 是输出的数组变量

endmodule

//-----------------------key0-----------------------
module key0(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 
 reg low_sw_r;
 
 always @(posedge clk )//上升沿
  low_sw_r <= low_sw;
 
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end

 assign ledout = ledout_r;
 
endmodule

//-----------------------key1-----------------------
module key1(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk )
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
 
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;

 end

 assign ledout = ledout_r;
 
endmodule

//-----------------------key2-----------------------
module key2(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
 
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end

 assign ledout = ledout_r;
 
endmodule

//-----------------------key3-----------------------
module key3(en,rst_n,clk,key,ledout);

 input clk;
 input rst_n;
 input en;
 input key;
 output ledout;

 reg low_sw;
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   low_sw <= 1'b1;
  else if(en)
   low_sw <= key;
 end
 
 reg low_sw_r;
 always @(posedge clk )
  low_sw_r <= low_sw;
 
 wire led_ctrl = low_sw_r & (!low_sw);
 
 reg ledout_r;
 
 always @(posedge clk or negedge rst_n)
 begin
  if (!rst_n)
   ledout_r <= 1'b0;
  else if(led_ctrl)
   ledout_r <= ~ledout_r;
 end

 assign ledout = ledout_r;
 
endmodule

我的引脚配置：

clk Input PIN_129 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
keyin[3] Input PIN_113 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
keyin[2] Input PIN_114 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
keyin[1] Input PIN_110 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
keyin[0] Input PIN_112 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
ledout[3] Output PIN_133 3 B3_N0 3.3-V LVTTL (default)  24mA (default)
ledout[2] Output PIN_134 3 B3_N0 3.3-V LVTTL (default)  24mA (default)
ledout[1] Output PIN_127 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
ledout[0] Output PIN_128 3 B3_N1 3.3-V LVTTL (default)  24mA (default)
rst_n Input PIN_30 1 B1_N1 3.3-V LVTTL (default)  24mA (default)
<<new node>>       
别人的编译好的东西运行在他的板子是好的（有视频），我把他的sof现在到我的板子上也是不行。我自己编译的也是不行。key不能控制相关led(参考别人代码)

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