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-- Quad D-Type Flip-flop

-- This example shows how a conditional signal assignment statement could be used to describe sequential logic(it is more common to use a process). 

-- The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part of the language. 

-- The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement. 

-- uses 1993 std VHDL





library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is  

   port(D : in std_logic_vector(3 downto 0);

         Q : out std_logic_vector(3 downto 0);

         CLRBAR, CLK : in std_logic);

end HCT175;



architecture VER1 of HCT175 is

begin

   Q <= (others => '0') when (CLRBAR = '0') 

            else D when rising_edge(CLK)

            else unaffected;

end VER1;